Study of oxide-based resistive memory device scaling : device integration, electrical measurements, electrothermal simulations

PhD start: October 2011; Duration: 3 ys

The Applicants :

The PhD Topic Description:

Context - In order to overcome the scaling limitations of floating-gate non-volatile memory technology (Flash memories) beyond the 22 nm node, the semiconductor industry is currently evaluating several alternatives. Resistive Memories (RRAM : Resistive Random Access Memory) are driving a huge effort in research, being considered highly promising in terms of scalability, high working speed and low power consumption.      

 Fig. 1 RRAM memory cells stacked within crossbar matrix. After M.-J. Lee et al., IEDM Tech. Dig. 771 (2007).

These devices generally implement binary transition metal oxides such as NiO, TiO2 and other oxide dielectrics such as HfO2, ZrO2, Ta2O5, Al2O3, CoOx. The working principle of the oxide–based RRAM is based on a reversible breakdown of the dielectric layer that leads to a deep resistance change in the device. At different resistance levels are associated with different logic values. However a full and detailed comprehension of the underlying physics is still missing. Such devices are candidates to address high-density storage (stacked 3D crossbar circuits as sketched in Fig.1) as well as embedded applications and potentially reconfigurable circuits.

PhD work - The main aim of the PhD will be the study of a back-end-of-line (BEOL) compatible oxide-based RRAM device based on dielectric metal oxides, consisting of device structure fabrications and electrical characterizations. Technology development will focus on the implementation of CMOS compatible process and integration schemes along with the study of materials to be exploited as active switching layer and electrical contact electrode.   The PhD work plan will include the following tasks:

1.    Prepare integration schemes for Si CMOS compatible to scalable oxide-based RRAM devices: the work will involve design of integration schemes with BEOL compatible processes and materials, and search for non-noble metal based inert electrodes. Memory cells with bit selection devices should be designed in order to adequately control local electric field and heating effects in scaled devices..

2.    Fabricate RRAM devices with the designed integration schemes by establishing the process flow that will utilize e-beam lithography for ultimate small geometry for the cells. The candidate will monitor each of the process steps in LETI clean room.

3.    Electrical characterization aimed at the assessment of device performances in DC and short pulsed switching (ns range) in order to improve materials and integration processes as well as advancement in resistive switching mechanism comprehension.   This will include both “on-state” and “off-state” current measurements at various temperatures and also low frequency noise measurements (in IMEP-LAHC) which will provide deeper insights on the switching mechanism.

4.    Modelling and theoretical work will complete the tasks panel. Multiphysics simulations (electrothermal, drift-diffusion) will be performed in order to evaluate scaling perspectives concerning electrical field and heating effects.

The PhD Framework

The PhD will be founded by the Nanosciences Foundation in the frame of the Prof. Nishi Chair of Excellence Project. The Prof. Nishi  Chair of Excellence Project deals with Resistive Memory Devices and aim to bring an important contribution to resistive memory technology assessment for new applications, especially for reconfigurable circuits, through the establishment of reliable electrical characterization methodologies, reliable physical models of switching elements for circuit design, proposition of reprogrammable circuits implementing resistive switching elements, proposition of new circuit architectures implementing nanoscale switching elements. The combination of the technological know-how and facilities of Leti, the electrical characterization knowledge of IMEP-LAHC with the scientific expertise of Prof. Nishi from Stanford University will allow to reach those targets.
The Phd degree will be delivered by the Grenoble Institute of Technology (Grenoble INP). The net salary for the Phd is about 1500 €/month during 36 months, including health care insurance (income tax not deduced).

The Laboratory

Under the direction of Prof. Nishi, the PhD work will be performed in the Advanced Memory Technologies Laboratory of CEA-LETI (http://www-leti.cea.fr/en), a world leader laboratory in the creation and transfer of innovation from technologies to applications within Europe. The student will work in strict collaboration with the IMEP-LAHC academic laboratory (http://imep-lahc.grenoble-inp.fr/index.jsp).  LETI and IMEP-LAHC are part of the Grenoble MINATEC innovation campus (http://www.minatec.com/en), which is home to 2,400 researchers, 1,200 students, and 600 technology transfer experts on a state-of-the-art 20-hectare campus offering 10,000 square meters of clean room space. MINATEC is located in the Grenoble-Isère French region, otherwise known as France’s Silicon Valley, A unique scientific, industrial and cultural environment, With its research centers, university campus, 500 foreign companies and 40,000 scientists, engineers and technicians employed in the area.

The PhD Advisors

The PhD Advisors

Prof. NISHI Yoshio

Stanford University

(650) 723-9508

Email:     Yoshio.nishi@stanford.edu

Dr. BUCKLEY Julien
Advanced Memory Technology Laboratory
CEA LETI MINATEC Campus
17 rue des Martyrs, 38054 Grenoble CEDEX 9
+33 4 38 78 46 57
Email : julien.buckley@cea.fr    

Dr. DE SALVO Barbara
Advanced Memory Technology Laboratory
CEA LETI MINATEC Campus
17 rue des Martyrs, 38054 Grenoble CEDEX 9
+33 4 38 78 64 97
Email : barbara.desalvo@cea.fr

Prof. GHIBAUDO Gérard
IMEP-LAHC MINATEC Campus
+33 4 38 78 48 94
Email : ghibaudo@minatec.inpg.fr