Challenges of ESD RF protections in advanced CMOS technologies

Thursday 8 décember 2011 from 1pm to 2pm

Amphithéâtre PHELMA, Bât. INP, MINATEC

Abstract:

The main purpose of this presentation is to discuss the challenge of RF ESD protections for the Advanced CMOS technologies. Today, it is well known that the ElectroStatic Discharge (ESD) protection is already a major challenge. This is due to the complexity of the technologies (High K metal Gate, sub-nanometric size, dual oxide…) and due to the complexity of System On Chip (SOC) (Mono-multi dice, multi powers, multi applications, multi balls …). After a short introduction on the technology Roadmap and SOC complexity, the ESD constraints are introduced. At this step, the main accent will be done on the integration context challenge. Afterwards, the focus will be on RF constraints coupled with ESD protections. Some approaches, results and silicon implementations are presented and evaluated.

Biography:

Philippe Galy is Senior Expert in micro-nano electronics at STMicrolectronics R&D Crolles France since 2005. He manages 4 groups in the Advanced Device Design & ESD Solutions (ADDES) team. Before, he was professor in engineer school during 10 years old. He has authored or co-authored more than 75 publications, 2 books and 20 patents. He holds a Ph.D. and H.D.R. (academic research supervisor).