There is widely shared concern today that as we approach future technology nodes of CMOS beyond sub-20nm, diminishing return in device performance and density combined with serious increase in on-chip power consumption would force us to seek for possible alternatives beyond simple scaling of the minimum geometry.
Applications of mechanical strain to MOSFET channel for improved transport characteristics, material alternatives for conductive channel of MOSFET such as germanium and/or III-V semiconductor, intensive study for partial replacement of on-chip interconnects with optical interconnect, new nonvolatile memory phenomena thereby feasibility of new memory devices such as resistive switching are only a part of such efforts in addition to global trend of going 3D devices and integration. Also mentioned should include a variety of “nano” materials such as carbon nanotube, graphene, topological insulator etc, which might capture unique positions in integrated circuit technology arsenal with further in-depth understanding and technological break-through for controlling their characteristics.

This talk will discuss a perspective of a variety of nanoelectronic devices to be integrated on silicon platform, and where they would likely be heading toward.